[Quantum-ms] [4/18 Seminar] EE X CISL: Ajay Balankutty (Principal Engineer, Intel)

[Columbia EE Events]

Hi all,

Sorry about the second email. The location for this meeting is cepsr 414
(instead of EE conference room). Thanks!

Best,
Tina

Tina (Xintian) Wang
Events & External Relations Manager
Department of Electrical Engineering
857-218-0454 (Mudd 1310)
LinkedIn: https://urldefense.proofpoint.com/v2/url?u=http-3A__www.linkedin.com_in_xintian-2Dwang1&d=DwIFaQ&c=009klHSCxuh5AI1vNQzSO0KGjl4nbi2Q0M1QLJX9BeE&r=SD-9ztpHDQVkXLFc0zdc9RZWqGhdQ2vAJZ0O73eMlt0&m=zmyKsPfmwRE5jWwRSfLWRTvXITWx5T49XO4k5zHjGYt9HlValSw9vv0fm6HLhq4w&s=5pFI2VyPn5sRGGmqHpJj3ABw6I_eJmU3wfUTG6eZ_iQ&e= 
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On Wed, Apr 2, 2025 at 11:52 Columbia EE Events <ee-events at ee.columbia.edu>
wrote:

> [image: Left-aligned blue cuee logo.png]
>
> *Please join us for EE x CISL Seminar on 4/18!*
>
> *When: *4/18 Friday, 2-3pm
> *Where: CEPSR 414*
> *Who: * Ajay Balankutty (Principal Engineer, Intel)
> *Title:* Architecting High-Speed SerDes Transceivers in Advanced CMOS
> Technologies
> *Host: *Peter R. Kinget
>
> *Abstract: *CMOS technology in the angstrom (Å) era of semiconductors
> continues to provide scaling benefits to digital systems (like CPUs and
> GPUs) and Analog/Mixed-signal IPs (like PLLs, data converters, wireline and
> wireless transceivers) by realizing more capable and power efficient
> designs. As always, a deep understanding of semiconductor and interconnect
> physics enables circuit designers to differentiate and exploit technology
> scaling fully. I will give an overview of an advanced CMOS process
> technology with nanoribbon (RibbonFET) with back-side power delivery, and
> some of the fundamental physics that that can influence circuit and
> architecture choices. We will then go over in detail SerDes transceiver
> trends, architecture advances and circuits evolution paired with CMOS
> scaling, with specific examples from our recent work in 100Gb/s and 200Gb/s
> links.
>
> *Bio: *Ajay Balankutty received his M.S. and Ph.D. from Columbia
> University in Electrical Engineering in 2010. He is currently a Principal
> Engineer, technical lead and manages SerDes development at Intel, where his
> group in develops the first Serial I/O transceivers in Intel’s latest
> process technology nodes that serves as a reference design for all foundry
> customers. His pathfinding team also develops the IP architecture and
> circuits for next generation Ethernet, OIF and PCIe standards. Since 2010,
> Ajay and his team developed 28Gb/s, 56Gb/s, 112Gb/s and 224Gb/s SerDes
> transceivers. In addition to SerDes design, he and his team performs system
> technology co-optimization (STCO) to ensure that CMOS scaling continues to
> provide benefits for analog/mixed-signal circuits and systems. Ajay has
> published over 25 papers in peer-reviewed conferences and journals and is a
> member of the Technical Program Committee of CICC.
>
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